#Altera quartus ii adder lab full
Lab 2 Introduction to VHDL Full Adder Structural VHDL Code Name the file FullAdder and click Save in the Save As dialog box. Copy and paste the following code into your new VHDL file, then save it by selecting File Create another new VHDL file following the directions in step 1 of task 2.Ĩ. LIBRARY ieee USE ieee.std_logic_1164.ALL ENTITY Gate_OR3 IS PORT (x: IN std_logic y: IN std_logic z: IN std_logic F: OUT std_logic) END Gate_OR3 ARCHITECTURE Gate_OR3_beh OF Gate_OR3 IS BEGIN PROCESS(x, y, z) BEGIN Fħ. Lab 2 Introduction to VHDL Three-Input OR Gate Behavioral VHDL Code This is a three-input OR Gate, written using Behavioral style VHDL. Name the file Or3 and click Save in the Save As dialog box. LIBRARY ieee USE ieee.std_logic_1164.ALL ENTITY Gate_And2 IS PORT (x: IN std_logic y: IN std_logic F: OUT std_logic) END Gate_And2 ARCHITECTURE Gate_And2_beh OF Gate_And2 IS BEGIN PROCESS(x, y) BEGIN FĦ. Lab 2 Introduction to VHDL Two-Input AND Gate Behavioral VHDL Code Name the file And2 and click Save in the Save As dialog box. Select: VHDL File from the Design Files list and click OK.Ģ. Task 2: Create, Add, and Compile Design Filesġ. Click Finish to complete the New Project Wizard. Click Next again as we will not be using any third party EDA tools.ħ. In the list of available devices, select EPC235F672C6. Select the family and Device Settings.įrom the pull-down menu labeled Family, select Cyclone II. Click Next again as we will not be adding any preexisting design files at this time.ĥ. Note: A window may pop up stating that the chosen working directory does not exist. Working Directory H:\Altera_Training\Lab2Ĭlick Next to advance to page 2 of the New Project Wizard.
Select the Working Directory and Project Name. If the opening splash screen is displayed, select: Create a New Project (New Project Wizard), otherwise from the Quartus II Menu Bar select: File New Project Wizard.ģ.
#Altera quartus ii adder lab windows
From the Windows Start Menu, select: All Programs Other Apps Altera Quartus II 9.1 Quartus II 9.1 (32-Bit)Ģ. The individual gates will be coded separately using behavioral style VHDL, and then stitched together using structural style VHDL to create the full adder.ġ. It consists of three two-input AND gates, two XOR gates, and one three-input OR gate. The outputs are four-bit sum Sum, and a carry-out output Cout.īelow is a detailed diagram of the full adder circuit used. The inputs are two four-bit numbers A and B, and an add/subtract selection input Sel. The component make-up includes four full adders and four XOR logic gates. Below is a schematic diagram of the complete circuit. The circuit you will create is a ripple-carry four-bit adder/subtractor using both behavioral and structural VHDL coding. In this lab you will design, test, and simulate a basic logic circuit using the Quartus II development software.
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